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cy2544/cy2548, cy2546 quad pll programmable clock generator with spread spectrum cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-12563 rev. *g revised december 21, 2010 quad pll programmable clock generator features four fully integrated phase locked loops (plls) input frequency range ? external crystal: 8 to 48 mhz for cy2544 and cy2546 ? external reference: 8 to 166 mhz clock reference clock input voltage range ? 2.5v, 3.0v, and 3.3v for cy2548 ? 1.8v for cy2544 and cy2546 wide operating output frequency range ? 3 to 166 mhz programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles vdd supply voltage options: ? 2.5v, 3.0v, and 3.3v for cy2544 and cy2548 ? 1.8v for cy2546 selectable output clock voltages: ? 2.5v, 3.0v, and 3.3v for cy2544 and cy2548 ? 1.8v for cy2546 frequency select feature with option to select eight different frequencies over nine clock outputs power down, output enable, and ss on/off controls low jitter, high accuracy outputs ability to synthesize nonstandard frequencies with fractional-n capability up to nine clock outputs with programmable drive strength glitch free outputs while frequency switching 24-pin qfn package commercial and industrial temperature ranges benefits multiple high performance plls allow synthesis of unrelated frequencies nonvolatile programming for personalization of pll frequencies, spread spectrum c haracteristics, drive strength, crystal load capacitance, and output frequencies application specific programmable emi reduction using spread spectrum for clocks programmable plls for system frequency margin tests meets critical timing requirements in complex system designs suitability for pc, consumer, portable, and networking applications capable of zero ppm frequency synthesis error uninterrupted system operati on during clock frequency switch application compatibility in standard and low power systems osc pll1 pll2 pll3 (ss) pll4 (ss) output dividers and drive strength control clk1 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 clkin fs 2 fs 1 fs 0 sson xout xin/ exclkin pd#/oe bank 1 bank 3 bank 2 mux and control logic crossbar switch logic block diagram [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 2 of 16 contents general description ......................................................... 5 four configurable plls .............................................. 5 input reference clocks .......... .............. .............. ......... 5 multiple power supplies ...... ........................................ 5 output bank settings .................................................. 5 output source selection ............................................. 5 spread spectrum control ............................................ 5 frequency select ........................................................ 6 glitch-free frequency switch ..................................... 6 pd#/oe mode ............................................................. 6 output drive strength .................................................. 6 generic configuration and custom frequency ........... 6 absolute maximum conditions ....................................... 7 recommended operating conditions ............................ 7 dc electrical specifications ............................................ 8 ac electrical specifications ............................................ 9 recommended crystal specification for smd package 9 test and measurement setup ........................................ 10 voltage and timing definitions ..................................... 10 recommended crystal specification for thru-hole package ......................................................... 10 ordering information ...................................................... 11 possible configurations ............................................. 11 ordering code definition .... ....................................... 12 package drawing and dimensions ............................... 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc solutions ......................................................... 16 [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 3 of 16 table 1. device selection guide figure 1. pin diagram ? cy2544/cy2548 24 ld qfn device crystal input excklkin input clkin input vdd vdd_clk_bx cy2544 yes 1.8 v lvcmos 2.5 v, 3.0 v, 3.3 v lvcm os 2.5 v, 3.0 v, 3.3 v 2.5 v, 3.0 v, 3.3 v cy2546 yes 1.8 v lvcmos 1.8 v lvcmos 1.8 v 1.8 v cy2548 no 2.5 v, 3.0 v, 3.3 v lvcmos 2.5 v, 3.0 v, 3. 3 v lvcmos 2.5 v, 3.0 v, 3.3 v 2.5 v, 3.0 v, 3.3 v c l k i n clk1 pd#oe cy2544 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd vdd_clk_b1 nc clk2 o e / f s 1 c l k 3 / f s 0 c l k 4 / f s 2 c l k 5 g n d clk6 vdd_clk_b 2 clk7/sson vdd_clk_b 3 clk8 gnd clk9 v d d x o u t x i n / e x c l k i n g n d 24ld qfn c l k i n clk1 pd#oe cy2548 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 g n d gnd vdd_clk_b1 nc clk2 o e / f s 1 c l k 3 / f s 0 c l k 4 / f s 2 c l k 5 g n d clk6 vdd_clk_b 2 clk7/sson vdd_clk_b 3 clk8 gnd c l k 9 v d d d n u e x c l k i n g n d 24ld qfn table 2. pin definition ? cy2544/cy2 548 (vdd = 2.5 v, 3.0 v or 3.3 v supply) pin number name io description 1 gnd power power supply ground 2 clk1 output programmable clock output. output voltage depends on vdd_clk_b1 voltage 3 vdd_clk_b1 power power supply for bank1, (clk1, clk2, clk3) outputs: 2.5 v/3.0 v/3.3 v 4 pd#/oe input multifunction programmable pin. output enable or power-down mode 5nc nc no connect 6 clk2 output programmable clock output. output voltage depends on vdd_clk_b 1 voltage 7 gnd power power supply ground 8 clk3/fs0 output/input multifunction programmable pin. programmable clock output clock or frequency select pin. output voltage of clk3 depends on vdd_clk_b 1 voltage 9 oe/fs1 input multifunction programmable pin. output enable or frequency select pin 10 clk4/fs2 output/input multifunction programmable pin. programmable clock output or frequency select input pin. output voltage of clk4 depends on vdd_clk_b 2 voltage 11 clk5 output programmable clock output. output voltage depends on vdd_clk_b 2 voltage 12 gnd power power supply ground 13 clk6 output programmable clock output . output voltage depends on vdd_clk_b 2 voltage 14 vdd_clk_b2 power power supply for bank2, (clk4, clk5, clk6) outputs. 2.5 v/3.0 v/3.3 v 15 clk7/sson output/input multifunction programmable pin. programmable clock output or spread spectrum on/off control input pin . output voltage of clk7 depends on bank3 voltage 16 vdd_clk_b3 power power supply for bank3, (clk7, clk8, clk9) outputs. 2.5 v/3.0 v/3.3 v [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 4 of 16 figure 2. pin diagram ? cy2546 24 ld qfn 17 clk8 output programmable output clock. output voltage depends on bank3 voltage 18 gnd power power supply ground 19 gnd power power supply ground 20 clk9 output programmable clock output . output voltage depends on vdd_clk_b 3 voltage 21 clkin input 2.5 v/3.0 v/3.3 v reference clock input. the signal level of clkin input must track vdd power supply on pin 22. 22 vdd power power supply. 2.5 v/3.0 v/3.3 v 23 xout output crystal output for cy2544 dnu output do not use this pin for cy2548 24 xin/exclkin input crystal input or 1.8 v external clock input for cy2544 exclkin input 2.5 v/3.0 v/3.3 v external clock input for cy2548 table 2. pin definition ? cy2544/cy2 548 (vdd = 2.5 v, 3.0 v or 3.3 v supply) (continued) pin number name io description c l k i n clk1 pd#oe cy2546 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd vdd_clk_b1 vdd clk2 o e / f s 1 c l k 3 / f s 0 c l k 4 / f s 2 c l k 5 g n d clk6 vdd_clk_b 2 clk7/sson vdd_clk_b 3 clk8 gnd clk9 v d d x o u t x i n / e x c l k i n g n d 24ld qfn table 3. pin definition ? cy2546 (vdd = 1.8 v supply) pin number name io description 1gndpower power supply ground 2 clk1 output programmable clock output. output voltage depends on vdd_clk_b1 voltage 3 vdd_clk_b1 power power supply for bank1, (clk1, clk2, clk3) outputs. 1.8v 4 pd#/oe input multifunction programmable pin. output enable or power down mode 5 vdd power power supply. 1.8 v 6 clk2 output programmable clock output. output voltage depends on vdd_clk_b1 voltage 7 gnd power power supply ground 8 clk3/fs0 output/input multifunction programmable pin. programmable clock output or frequency select input pin. output voltage of clk3 depends on vdd_clk_b1 voltage 9 oe/fs1 input multifunction programmable pin. output enable or frequency select pin 10 clk4/fs2 output/input multifunction programmable pin. programmable clock output or frequency select input pin. output voltage of clk4 depends on vdd_clk_b2 voltage 11 clk5 output programmable clock output. output voltage depends on vdd_clk_b2 voltage [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 5 of 16 general description four configurable plls the cy2544, cy2548 and cy2546 have four programmable plls that can be used to generate output frequencies ranging from 3 to 166 mhz. the advantage of having four plls is that a single device generates up to four independent frequencies from a single crystal. input reference clocks the input to the cy2544, cy2548 and cy2546 can be either a crystal or a clock signal. the input frequency range for crystal (xin) is 8 mhz to 48 mhz and that for external reference clock (exclkin) is 8 mhz to 166 mhz. the voltage range for the reference clock input of cy2548 is 2.5 v/3.0 v/3.3 v while that for cy2544 and cy2546 is 1.8 v. this gives user an option for this device to be compatible for different input clock voltage levels in the system. there is provision for a secondary reference clock input, clkin with applied frequency range of 8 mhz to 166 mhz. when clkin signal at pin 21 is used as a reference input to the pll, a valid signal at exclkin (as specified in the ac and dc electrical specification table) must be present for the devices to operate properly. multiple power supplies these devices are designed to op erate at internal supply voltage of 1.8 v. in the case of the hi gh voltage part (cy2544/cy2548), an internal regulator is used to generate 1.8 v from the 2.5 v/3.0 v/3.3 v vdd supply voltage at pin 22. for the low voltage part (cy2546), this internal regulator is bypassed and 1.8 v at vdd pin 22 is directly used. output bank settings there are nine clock outputs grouped in three output driver banks. the bank 1, bank 2, and bank 3 correspond to (clk1, clk2, clk3), (clk4, clk5, clk6), and (clk7, clk8, clk9) respectively. separate power supplies are used for each of these banks and they can be any of 2.5 v, 3.0 v, or 3.3 v for cy2544/cy2548 and 1.8 v for cy2546 giving user multiple choice of output clock voltage levels. output source selection these devices have programmable input sources for each of its nine clock outputs (clk1?9). there are six available clock sources for these outputs. these clock sources are: xin/exclkin, clkin, p ll1, pll2, pll3, or pll4. output clock source selection is done using fo ur out of six crossbar switch. thus, any one of these six available clock sources can be arbitrarily selected for the clock outputs. this gives user a flexibility to have up to four independent clock outputs. spread spectrum control two of the four plls (pll3 and pll4) have spread spectrum capability for emi reduction in the system. the device uses a cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the pll. the spread spectrum feature can be turned on or off using a multifunction control pin (clk7/sson). it can be programmed to either center spread range fr om 0.125% to 2.50% or down spread range from ?0.25% to ?5.0% with lexmark or linear profile. 12 gnd power power supply ground 13 clk6 output programmable clock output. output voltage depends on vdd_clk_b2 voltage 14 vdd_clk_b2 power power supply for bank2, (clk4, clk5, clk6) outputs. 1.8 v 15 clk7/sson output/input multifunction programmable pin. programmable clock output or spread spectrum on/off control input pin . output voltage of clk7 depends on vdd_clk_b3 voltage 16 vdd_clk_b3 power power supply for bank3, (clk7, clk8, clk9) outputs. 1.8 v 17 clk8 output programmable clock output. output voltage depends on vdd_clk_b3 voltage 18 gnd power power supply ground 19 gnd power power supply ground 20 clk9 output programmable clock output. output voltage depends on vdd_clk_b3 voltage 21 clkin input external 1.8 v low voltage reference clock input 22 vdd power power supply. 1.8 v 23 xout output crystal output 24 xin/exclkin input crystal input or 1.8 v external clock input table 3. pin definition ? cy2546 (vdd = 1.8 v supply) (continued) pin number name io description [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 6 of 16 frequency select there are three multifunction frequency select pins (fs0, fs1 and fs2) that provide an option to select eight different sets of frequencies among each of the four plls. each output has programmable output divider options. glitch-free frequency switch when the frequency select pin (fs) is used to switch frequency, the outputs are glitch-free provid ed frequency is switched using output dividers. th is feature enables uninterrupt ed system operation while clock frequency is being switched. pd#/oe mode pd#/oe (pin 4) can be programmed to operate as either power down (pd#) or output enable (oe) mode. pd# is a low-true input. if activated it shuts off the entire chip, resulting in minimum power consumption for the device. setting this signal high brings the device in the operational mode with default register settings. when this pin is programmed as output enable (oe), clock outputs can be enabled or disabled using oe (pin 4). individual clock outputs can be programmed to be sensitive to this oe pin. output drive strength the dc drive strength of the individual clock output can be programmed for different values. ta b l e 4 shows the typical rise and fall times for different drive strength settings. generic configuration and custom frequency there is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. the devices, cy2544, cy2548 and cy2546 can be custom programmed to any desired frequ encies and listed features. for customer specific programming, please contact local cypress field application engineer (fae) or sales representative. table 4. output drive strength output drive strength rise/fall time (ns) (typical value) low 6.8 mid low 3.4 mid high 2.0 high 1.0 table 4. output drive strength output drive strength rise/fall time (ns) (typical value) [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 7 of 16 absolute maximum conditions parameter description condition min max unit v dd supply voltage for cy2544/cy2548 ?0.5 4.5 v v dd supply voltage for cy2546 ?0.5 2.6 v v dd_clk_bx output bank supply voltage ?0.5 4.5 v v in input voltage for cy2544/cy2548 relative to v ss ?0.5 v dd +0.5 v v in input voltage for cy2546 relative to v ss ?0.5 2.2 v t s temperature, storage non runctional ?65 +150 c esd hbm esd protection (human body model) je dec eia/jesd22-a114-e 2000 ? volts ul-94 flammability rating v-0 at 1/8 in. ? 10 ppm msl moisture sensitivity level 3 recommended oper ating conditions parameter description min typ max unit v dd vdd operating voltage for cy2544/cy2548 2.25 ? 3.60 v v dd vdd operating voltage for cy2546 1.65 1.8 1.95 v v dd_clk_bx output driver voltage for bank 1, 2 and 3 1.65 ? 3.60 v t ac commercial ambient temperature 0?+70c t ai industrial ambient temperature ?40 -- +85 c c load maximum load capacitance ??15pf t pu power up time for all v dd to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 8 of 16 dc electrical specifications parameter description conditions min typ max unit v ol output low voltage i ol = 2 ma, drive str ength = [00] ? ? 0.4 v i ol = 3 ma, drive strength = [01] i ol = 7 ma, drive strength = [10] i ol = 12 ma, drive strength = [11] v oh output high voltage i oh = ?2 ma, drive strength = [00] v dd_clk_bx ? 0.4 ??v i oh = ?3 ma, drive strength = [01] i oh = ?7 ma, drive strength = [10] i oh = ?12 ma, drive strength = [11] v il1 input low voltage of pd#/oe, fs0, fs1, fs2 and sson ???0.2 v dd v v il2 input low voltage of clkin for cy2544/cy2548 ???0.1 v dd v v il3 input low voltage of exclkin for cy2544 ? ? ? 0.15 v v il4 input low voltage of exclkin for cy2548 ? ? ? 0.1 v dd v v il5 input low voltage of clkin, exclkin for cy2546 ???0.1 v dd v v ih1 input high voltage of pd#/oe, fs0, fs1, fs2 and sson ? 0.8 v dd ??v v ih2 input high voltage of clkin for cy2544/cy2548 ? 0.9 v dd ??v v ih3 input high voltage of exclkin for cy2544 ? 1.6 ? 2.2 v v ih4 input high voltage of exclkin for cy2548 ? 0.9 v dd ??v v ih5 input high voltage of clkin, exclkin for cy2546 ? 0.9 v dd ??v i il1 input low current of pd#/oe and fs1 v il = 0v ? ? 10 a i ih1 input high current of pd#/oe and fs1 v ih = v dd ??10a i il2 input low current of sson, fs0, and fs2 v il = 0v (internal pull dn = 160k typ) ? ? 10 a i ih2 input high current of sson, fs0, and fs2 v ih = v dd (internal pull dn = 160k typ) 14 ? 36 a r dn pull down resistor of sson, fs0, fs2 and clocks (clk1-clk9) in off-state clock outputs in off-state by setting pd# = low 100 160 250 k ? i dd [1,2] supply current for cy2546 pd# = high, no load ?20?ma supply current for cy2544/cy2548 pd# = high, no load ?22?ma i dds [1] standby current pd# = low ?3?a c in [1] input capacitance sson, clkin, pd#/oe, fs0, fs1, and fs2 pins ??7pf notes 1. guaranteed by design but not 100% tested. 2. configuration dependent. [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 9 of 16 ac electrical specifications parameter description conditions min typ max unit f in (crystal) crystal frequency, xin ? 8 ? 48 mhz f in (clock) input clock frequency (clkin or exclkin) ? 8 ? 166 mhz f clk output clock frequency ? 3 ? 166 mhz dc1 output duty cycle, all clocks except ref out duty cycle is defined in figure 4 ; t 1 /t 2 , measured at 50% of v dd _ clk_bx 45 50 55 % dc2 ref out clock duty cycle ref in min 45%, max 55% 40 ? 60 % t rf1 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 5 , c load = 15 pf, drive strength [00] ?6.8?ns t rf2 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 5 , c load = 15 pf, drive strength [01] ?3.4?ns t rf3 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 5 , c load = 15 pf, drive strength [10] ?2.0?ns t rf4 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 5 , c load = 15 pf, drive strength [11] ?1.0?ns t ccj [3,4] cycle-to-cycle jitter (peak) configuration dependent. see ta b l e 5 ?150? ps t lock [3] pll lock time measured from 90% of the applied power supply level ?13ms table 5. configuration example for c-c jitter ref. freq. (mhz) clk1 output clk2 output clk3 output clk4 output clk5 output freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) 14.3181 8.0 134 166 103 48 92 74.25 81 not used 19.2 74.25 99 166 94 8 91 27 110 48 75 27 48 67 27 109 166 103 74.25 97 not used 48 48 93 27 123 166 137 166 138 8 103 recommended crystal spec ification for smd package parameter description range 1 range 2 range 3 unit f in crystal frequency 8 ? 14 14 ? 28 28 ? 48 mhz r1 maximum motional resistance (esr) 135 50 30 ? cl parallel load capacitance (see note 3 below) 8 ? 18 8 ? 14 8 ? 12 pf dl(max) maximum crystal drive level 300 300 300 w notes 3. guaranteed by design but not 100% tested 4. configuration dependent [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 10 of 16 test and measurement setup figure 3. test and measurement setup voltage and timing definitions figure 4. duty cycle definition figure 5. rise time = t rf , fall time = t rf note 5. cy2544, cy2548 and cy 2546 have internal cryst al load capac itance (cl) adju stment feature. recommended crystal specific ation for thru-hole package parameter [5] description range 1 range 2 range 3 unit f in crystal frequency 8 ? 14 14 ? 24 24 ? 32 mhz r1 maximum motional resistance (esr) 90 50 30 ? cl parallel load capacitance (see note 3 below) 8 ? 18 8 ? 12 8 ? 12 pf dl(max) maximum crystal drive level 1000 1000 1000 w 0.1 ? f v dd outputs c load gnd dut clock output v dd_clk_b x 50% of v dd_clk_bx 0v t 1 t 2 clock output t rf t rf v dd_clk_bx 80% of v dd_clk_bx 20% of v dd_clk_bx 0v [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 11 of 16 ordering information part number type [6] package supply voltage operating range pb-free cy2544c field programmable 24-pin qfn 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2544ct field programmable 24-pin qfn -tape and reel 2.5 v, 3.0v or 3.3 v commercial, 0 c to 70 c cy2548c field programmable 24-pin qfn 2.5 v, 3.0v or 3.3 v commercial, 0 c to 70 c cy2548ct field programmable 24-pin qfn -tape and reel 2.5 v, 3.0v or 3.3 v commercial, 0 c to 70 c cy2546c field programmable 24-pin qfn 1.8 v commercial, 0 c to 70 c cy2546ct field programmable 24-pin qfn -tape and reel 1.8 v commercial, 0 c to 70 c cy2544i field programmable 24-pin qfn 2.5 v, 3. 0 v or 3.3 v industrial, -40 c to +85 c cy2544it field programmable 24-pin qfn -tape and reel 2. 5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2548i field programmable 24-pin qfn 2.5 v, 3. 0 v or 3.3 v industrial, -40 c to +85 c cy2548it field programmable 24-pin qfn -tape and reel 2. 5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2546i field programmable 24-pin qfn 1.8 v industrial, -40 c to +85 c cy2546it field programmable 24-pin qfn -tape and reel 1.8 v industrial, -40 c to +85 c programmer cy3675-clkmaker1 programming kit cy3675-qfn24a socket adapter board, for programming cy2544 and cy2548 [7] some product offerings are factory programmed custom er specific devices with customized part numbers. the possible configurations table shows the available device types, but not complete part numbers. contact your local cypress f ae of sales representative for more information. possible configurations part number [8] type [6] package supply voltage operating range pb-free cy2544cxxx factory programmed 24-pin qfn 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2544cxxxt factory programmed 24-pin qf n -tape and reel 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2548cxxx factory programmed 24-pin qfn 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2548cxxxt factory programmed 24-pin qf n -tape and reel 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2546cxxx factory programmed 24-pin qfn 1.8 v commercial, 0 c to 70 c cy2546cxxxt factory programmed 24-pin qfn -tape and reel 1.8 v commercial, 0 c to 70 c cy2544ixxx factory programmed 24-pin qfn 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2544ixxxt factory programmed 24-pin qf n -tape and reel 2.5 v, 3.0 v or 3.3 v industrial, -4 0 c to +85 c cy2548ixxx factory programmed 24-pin qfn 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2548ixxxt factory programmed 24-pin qf n -tape and reel 2.5 v, 3.0 v or 3.3 v industrial, -4 0 c to +85 c cy2546ixxx factory programmed 24-pin qfn 1 .8 v industrial, -40 c to +85 c CY2546IXXXT factory programmed 24-pin qfn -tape and reel 1.8 v industrial , -40 c to +85 c notes 6. field programmable devices are shipped unprogrammed, and must be programmed before being installed on a board. factory progra mmed devices are shipped fully configured and ready to install on a board. 7. the cy3675-qfn24a cannot be used to program the cy2546. 8. ?xxx? is a variable that denotes a specif ic device configuration. fo r more details, contact your local cypress fae or cypress sales representative. [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 12 of 16 ordering code definition cy254x c/i marketing code: cy2544/6/8 = device number customer specific identification code xxx t package type: (t= tape and reel) temperature code (c=commercial or i=industrial) - [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 13 of 16 package drawing and dimensions figure 6. 24-ld qfn 4x4 mm (subcon punch type pkg with 2.49x2.49 epad) lf24a/ly24a 51-85203 *b [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 14 of 16 acronyms document conventions units of measure acronym description dl drive level dnu do not use dut device under test emi electromagnetic interference esd electrostatic discharge fae field application engineer fs frequency select jedec eia joint electron devices engineering council electronic industries alliance lvcmos low voltage complemetary metal oxide semiconductor oe output enable osc oscillator pd power down pll phase locked loop ppm parts per million ss spread spectrum ssc spread spectrum clock sson spread spectrum on symbol unit of measure c degrees celsius ff femtofarads ma milliampere mhz megahertz ? s microseconds ms millisecond ? w microwatts ns nanoseconds pf picofarads ppm parts per million ps picoseconds v volts ? ohms w watts [+] feedback
cy2544/cy2548, cy2546 document #: 001-12563 rev. *g page 15 of 16 document history page document title: cy2544/cy2548 cy2546 quad pll pr ogrammable clock generator with spread spectrum document number: 001-12563 revision ecn orig. of change submission date description of change ** 690257 rgl see ecn new datasheet *a 790516 rgl see ecn separated the pin configuration drawing into two to show the difference between cy2544 and cy2546 pinouts. changed the idd from 22 ma maximum to 25 ma typical changed i ilsr internal pull down from 100k to 160k changed i ihsr internal pull down from 100k to 160k and changed the maximum value from 10 ? a to 25 ? a changed i ilpdoe to no internal pull up and changed the maximum value from 10 ? a to 1 ? a changed i ihpdoe to no internal pull up *b 1508943 rgl/aesa see ecn changed the i ilsr maximum value to 10 ua changed the i ilpdoe and i ihpdoe values to a minimum of 1 ? a to a maximum of 10 ? a removed preliminary from title page changed the i ihpd from 1 ua to 10 ua changed the i ilsr from 1 ua to 10 ua added new i dds value = 3ua added new c-c jitter typical values, deleted long term jitter values deleted generic part numbers from ordering information added new device and specification for high ref input voltage part, cy2548 changed i2c tsu specification from 100ns to 250 ns changed esd spec from mil-std to jedec combined vdd operating condition spec for cy2545 to a single vdd spec in dc spec.: fs1 pin has no pull down resistor added device selection table 1 removed c0 from crystal spec *c 2748211 tsai 08/10/09 posting to external web. *d 2764011 cxq 09/15/09 fixed typo in ordering information table ? changed cy2548cxxx and cy2548cxxxt to cy2548ixxx and cy2548ixxxt for industrial temp parts. *e 2899758 kvm 03/26/10 updated ordering information table. updated package diagram updated copyright section. *f 2969587 kvm 07/09/2010 minor change: matched spec title on the first page to document history page. added "with spread spect rum" in first page title. *g 3115710 bash 12/21/2010 added ordering code definition , acronyms and units of measure table. [+] feedback
document #: 001-12563 rev. *g revised december 21, 2010 page 16 of 16 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2544/cy2548, cy2546 ? cypress semiconductor corporation, 2007-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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